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| Features * High Performance, Low Power AVR(R) 8-Bit Microcontroller * Advanced RISC Architecture - 135 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation - Up to 16 MIPS Throughput at 16 MHz - On-Chip 2-cycle Multiplier Non-volatile Program and Data Memories - 64/128K Bytes of In-System Self-Programmable Flash * Endurance: 100,000 Write/Erase Cycles - Optional Boot Code Section with Independent Lock Bits * USB Bootloader programmed by default in the Factory * In-System Programming by On-chip Boot Program hardware activated after reset * True Read-While-Write Operation * All supplied parts are preprogramed with a default USB bootloader - 2K/4K (64K/128K Flash version) Bytes EEPROM * Endurance: 100,000 Write/Erase Cycles - 4K/8K (64K/128K Flash version) Bytes Internal SRAM - Up to 64K Bytes Optional External Memory Space - Programming Lock for Software Security JTAG (IEEE std. 1149.1 compliant) Interface - Boundary-scan Capabilities According to the JTAG Standard - Extensive On-chip Debug Support - Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface USB 2.0 Full-speed/Low-speed Device and On-The-Go Module - Complies fully with: - Universal Serial Bus Specification REV 2.0 - On-The-Go Supplement to the USB 2.0 Specification Rev 1.0 - Supports data transfer rates up to 12 Mbit/s and 1.5 Mbit/s USB Full-speed/Low Speed Device Module with Interrupt on Transfer Completion - Endpoint 0 for Control Transfers : up to 64-bytes - 6 Programmable Endpoints with IN or Out Directions and with Bulk, Interrupt or Isochronous Transfers - Configurable Endpoints size up to 256 bytes in double bank mode - Fully independant 832 bytes USB DPRAM for endpoint memory allocation - Suspend/Resume Interrupts - Power-on Reset and USB Bus Reset - 48 MHz PLL for Full-speed Bus Operation - USB Bus Disconnection on Microcontroller Request USB OTG Reduced Host : - Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for OTG dual-role devices - Provide Status and control signals for software implementation of HNP and SRP - Provides programmable times required for HNP and SRP Peripheral Features - Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode - Two16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode * 8-bit Microcontroller with 64/128K Bytes of ISP Flash and USB Controller AT90USB646 AT90USB647 AT90USB1286 AT90USB1287 * * * Summary * * 7593KS-AVR-11/09 * * * * * - Real Time Counter with Separate Oscillator - Four 8-bit PWM Channels - Six PWM Channels with Programmable Resolution from 2 to 16 Bits - Output Compare Modulator - 8-channels, 10-bit ADC - Programmable Serial USART - Master/Slave SPI Serial Interface - Byte Oriented 2-wire Serial Interface - Programmable Watchdog Timer with Separate On-chip Oscillator - On-chip Analog Comparator - Interrupt and Wake-up on Pin Change Special Microcontroller Features - Power-on Reset and Programmable Brown-out Detection - Internal Calibrated Oscillator - External and Internal Interrupt Sources - Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby I/O and Packages - 48 Programmable I/O Lines - 64-lead TQFP and 64-lead QFN Operating Voltages - 2.7 - 5.5V Operating temperature - Industrial (-40C to +85C) Maximum Frequency - 8 MHz at 2.7V - Industrial range - 16 MHz at 4.5V - Industrial range 2 AT90USB64/128 7593KS-AVR-11/09 AT90USB64/128 1. Pin Configurations Figure 1-1. Pinout AT90USB64/128-TQFP PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF4 (ADC4/TCK) PF7 (ADC7/TDI) PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PA0 (AD0) PA1 (AD1) 50 64 63 62 61 60 59 58 57 56 55 54 53 52 51 (INT.6/AIN.0) PE6 (INT.7/AIN.1/UVcon) PE7 UVcc DD+ UGnd UCap VBus (IUID) PE3 (SS/PCINT0) PB0 (PCINT1/SCLK) PB1 (PDI/PCINT2/MOSI) PB2 (PDO/PCINT3/MISO) PB3 (PCINT4/OC.2A) PB4 (PCINT5/OC.1A) PB5 (PCINT6/OC.1B) PB6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 INDEX CORNER 49 PA2 (AD2) AVCC AREF GND GND VCC 48 47 46 45 44 43 42 PA3 (AD3) PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PE2 (ALE/HWB) PC7 (A15/IC.3/CLKO) PC6 (A14/OC.3A) PC5 (A13/OC.3B) PC4 (A12/OC.3C) PC3 (A11/T.3) PC2 (A10) PC1 (A9) PC0 (A8) PE1 (RD) PE0 (WR) AT90USB90128/64 TQFP64 41 40 39 38 37 36 35 34 33 VCC GND XTAL2 RESET XTAL1 (OC0B/SCL/INT0) PD0 (RXD1/INT2) PD2 (TXD1/INT3) PD3 (XCK1) PD5 (ICP1) PD4 (T1) PD6 (INT4/TOSC1) PE4 (INT.5/TOSC2) PE5 (PCINT7/OC.0A/OC.1C) PB7 (OC2B/SDA/INT1) PD1 (T0) PD7 3 7593KS-AVR-11/09 Figure 1-2. Pinout AT90USB64/128-QFN PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF4 (ADC4/TCK) PF7 (ADC7/TDI) PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PA0 (AD0) 51 PA1 (AD1) 50 64 63 62 61 58 55 54 53 52 60 59 57 56 (INT.6/AIN.0) PE6 (INT.7/AIN.1/UVcon) PE7 UVcc DD+ UGnd UCap VBus (IUID) PE3 (SS/PCINT0) PB0 (PCINT1/SCLK) PB1 (PDI/PCINT2/MOSI) PB2 (PDO/PCINT3/MISO) PB3 (PCINT4/OC.2A) PB4 (PCINT5/OC.1A) PB5 (PCINT6/OC.1B) PB6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 17 18 19 21 22 23 24 25 26 27 28 29 30 31 32 49 PA2 (AD2) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AVCC AREF GND GND VCC PA3 (AD3) PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PE2 (ALE/HWB) PC7 (A15/IC.3/CLKO) PC6 (A14/OC.3A) PC5 (A13/OC.3B) PC4 (A12/OC.3C) PC3 (A11/T.3) PC2 (A10) PC1 (A9) PC0 (A8) PE1 (RD) PE0 (WR) INDEX CORNER AT90USB128/64 (64-lead QFN top view) VCC GND XTAL2 XTAL1 (ICP1) PD4 (TXD1/INT3) PD3 (XCK1) PD5 RESET (RXD1/INT2) PD2 (T1) PD6 (OC0B/SCL/INT0) PD0 (INT4/TOSC1) PE4 (INT.5/TOSC2) PE5 Note: The large center pad underneath the MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board. 1.1 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 2. Overview The AT90USB64/128 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the 4 AT90USB64/128 7593KS-AVR-11/09 (PCINT7/OC.0A/OC.1C) PB7 (OC2B/SDA/INT1) PD1 (T0) PD7 AT90USB64/128 AT90USB64/128 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Block Diagram Figure 2-1. XT AL1 XT AL2 PF7 - PF0 PA7 - P A0 PC7 - PC0 VCC GND POR TF DRIVERS POR TA DRIVERS POR TC DRIVERS DATA REGISTER PORT F DATA DIR. REG. PORT F DATA REGISTER PORT A DATA DIR. REG. PORT A DATA REGISTER PORT C 8-BIT DA TA BUS DATA DIR. REG. PORT C AVCC AGND AREF JTAG TAP PROGRAM COUNTER ADC POR - BOD RESET INTERNAL OSCILLA TOR CALIB. OSC ST ACK POINTER WATCHDOG TIMER OSCILLA TOR ON-CHIP DEBUG PROGRAM FLASH SRAM MCU CONTROL REGISTER TIMING AND CONTROL BOUNDARYSCAN INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS X Y Z TIMER/ COUNTERS PROGRAMMING LOGIC INSTRUCTION DECODER INTERRUPT UNIT CONTROL LINES ALU EEPROM PLL ST ATUS REGISTER USART1 SPI USB TWO-WIRE SERIAL INTERFACE ANALOG COMP ARATOR DATA REGISTER PORTE DATA DIR. REG. PORTE DATA REGISTER PORTB DATA DIR. REG. PORTB DATA REGISTER PORTD DATA DIR. REG. PORTD + - POR TE DRIVERS POR TB DRIVERS POR TD DRIVERS PE7 - PE0 PB7 - PB0 PD7 - PD0 RESET 5 7593KS-AVR-11/09 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The AT90USB64/128 provides the following features: 64/128K bytes of In-System Programmable Flash with Read-While-Write capabilities, 2K/4K bytes EEPROM, 4K/8K bytes SRAM, 48 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, one USART, a byte oriented 2-wire Serial Interface, a 8-channels, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The device is manufactured using Atmel's high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel AT90USB64/128 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The AT90USB64/128 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 6 AT90USB64/128 7593KS-AVR-11/09 AT90USB64/128 2.2 2.2.1 Pin Descriptions VCC Digital supply voltage. 2.2.2 GND Ground. 2.2.3 AVCC Analog supply voltage. 2.2.4 Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the AT90USB64/128 as listed on page 79. 2.2.5 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B has better driving capabilities than the other ports. Port B also serves the functions of various special features of the AT90USB64/128 as listed on page 80. 2.2.6 Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the AT90USB64/128 as listed on page 83. 2.2.7 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the AT90USB64/128 as listed on page 84. 7 7593KS-AVR-11/09 2.2.8 Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the AT90USB64/128 as listed on page 87. 2.2.9 Port F (PF7..PF0) Port F serves as analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs. Port F also serves the functions of the JTAG interface. 2.2.10 DUSB Full speed / Low Speed Negative Data Upstream Port. Should be connected to the USB Dconnector pin with a serial 22 Ohms resistor. 2.2.11 D+ USB Full speed / Low Speed Positive Data Upstream Port. Should be connected to the USB D+ connector pin with a serial 22 Ohms resistor. 2.2.12 UGND USB Pads Ground. 2.2.13 UVCC USB Pads Internal Regulator Input supply voltage. 2.2.14 UCAP USB Pads Internal Regulator Output supply voltage. Should be connected to an external capacitor (1F). 2.2.15 VBUS USB VBUS monitor and OTG negociations. 2.2.16 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 8-1 on page 58. Shorter pulses are not guaranteed to generate a reset. 2.2.17 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 8 AT90USB64/128 7593KS-AVR-11/09 AT90USB64/128 2.2.18 XTAL2 Output from the inverting Oscillator amplifier. 2.2.19 AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 2.2.20 AREF This is the analog reference pin for the A/D Converter. 3. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. These code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". 9 7593KS-AVR-11/09 4. Register Summary Address (0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4) (0xC3) (0xC2) (0xC1) (0xC0) (0xBF) Name Reserved Reserved Reserved Reserved Reserved Reserved OTGTCON UPINT UPBCHX UPBCLX UPERRX UEINT UEBCHX UEBCLX UEDATX UEIENX UESTA1X UESTA0X UECFG1X UECFG0X UECONX UERST UENUM UEINTX Reserved UDMFN UDFNUMH UDFNUML UDADDR UDIEN UDINT UDCON OTGINT OTGIEN OTGCON Reserved Reserved USBINT USBSTA USBCON UHWCON Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved UDR1 UBRR1H UBRR1L Reserved UCSR1C UCSR1B UCSR1A Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bit 7 - Bit 6 PAGE Bit 5 - Bit 4 PINT7:0 Bit 3 - Bit 2 - Bit 1 VALUE Bit 0 - Page - COUNTER1:0 - - PBYCT7:0 CRC16 TIMEOUT EPINT6:0 BYCT7:0 DAT7:0 PID PBYCT10:8 DATAPID BYCT10:8 DATATGL - - FLERRE CFGOK NAKINE OVERFI UNDERFI EPSIZE2:0 NAKOUTE - RXSTPE - RXOUTE CTRLDIR STALLEDE TXINE CURRBK1:0 NBUSYBK1:0 ALLOC DTSEQ1:0 EPBK1:0 - EPTYPE1:0 STALLRQ STALLRQC RSTDT EPRST6:0 EPDIR EPEN EPNUM2:0 FIFOCON NAKINI RWAL NAKOUTI FNCERR FNUM10:8 FNUM7:0 ADDEN UPRSME UPRSMI EORSME EORSMI STOI STOE HNPREQ WAKEUPE WAKEUPI HNPERRI HNPERRE SRPREQ UADD6:0 EORSTE EORSTI ROLEEXI ROLEEXE SRPSEL SOFE SOFI LSM BCERRI BCERRE VBUSHWC RMWKUP VBERRI VBERRE VBUSREQ SUSPE SUSPI DETACH SRPI SRPE VBUSRQC RXSTPI RXOUTI STALLEDI TXINI IDTI SPEED USBE UIMOD HOST UIDE FRZCLK OTGPADE UVCONE ID IDTE VBUSTI VBUS VBUSTE UVREGE UMSEL11 RXCIE1 RXC1 - UMSEL10 TXCIE1 TXC1 - UPM11 UDRIE1 UDRE1 - UPM10 RXEN1 FE1 - - - - - USART1 I/O Data Register USART1 Baud Rate Register High Byte USBS1 TXEN1 DOR1 UCSZ11 UCSZ12 PE1 UCSZ10 RXB81 U2X1 UCPOL1 TXB81 MPCM1 USART1 Baud Rate Register Low Byte 10 AT90USB64/128 7593KS-AVR-11/09 AT90USB64/128 Address (0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) (0x7D) Name Reserved TWAMR TWCR TWDR TWAR TWSR TWBR Reserved ASSR Reserved OCR2B OCR2A TCNT2 TCCR2B TCCR2A UPDATX UPIENX UPCFG2X UPSTAX UPCFG1X UPCFG0X UPCONX UPRST UPNUM UPINTX UPINRQX UHFLEN UHFNUMH UHFNUML UHADDR UHIEN UHINT UHCON OCR3CH OCR3CL OCR3BH OCR3BL OCR3AH OCR3AL ICR3H ICR3L TCNT3H TCNT3L Reserved TCCR3C TCCR3B TCCR3A Reserved Reserved OCR1CH OCR1CL OCR1BH OCR1BL OCR1AH OCR1AL ICR1H ICR1L TCNT1H TCNT1L Reserved TCCR1C TCCR1B TCCR1A DIDR1 DIDR0 - Bit 7 TWAM6 TWINT TWA6 TWS7 - Bit 6 TWAM5 TWEA TWA5 TWS6 EXCLK - Bit 5 TWAM4 TWSTA TWA4 TWS5 AS2 - Bit 4 TWAM3 TWSTO TWA3 TWS4 TCN2UB - Bit 3 TWAM2 TWWC TWA2 TWS3 OCR2AUB - Bit 2 TWAM1 TWEN TWA1 OCR2BUB - Bit 1 TWAM0 TWA0 TWPS1 TCR2AUB - Bit 0 TWIE TWGCE TWPS0 TCR2BUB - Page 2-wire Serial Interface Data Register 2-wire Serial Interface Bit Rate Register Timer/Counter2 Output Compare Register B Timer/Counter2 Output Compare Register A Timer/Counter2 (8 Bit) FOC2A COM2A1 FLERRE CFGOK FOC2B COM2A0 NAKEDE OVERFI COM2B1 UNDERFI PSIZE2:0 PTYPE1:0 PFREEZE PTOKEN1:0 INMODE RSTDT PRST6:0 PNUM2:0 FIFOCON NAKEDI RWAL PERRI TXSTPI INRQ7:0 FLEN7:0 FNUM10:8 FNUM7:0 HADD6:0 HWUPE HWUPI HSOFE HSOFI RXRSME RXRSMI RSMEDE RSMEDI RSTE RSTI RESUME Timer/Counter3 - Output Compare Register C High Byte Timer/Counter3 - Output Compare Register C Low Byte Timer/Counter3 - Output Compare Register B High Byte Timer/Counter3 - Output Compare Register B Low Byte Timer/Counter3 - Output Compare Register A High Byte Timer/Counter3 - Output Compare Register A Low Byte Timer/Counter3 - Input Capture Register High Byte Timer/Counter3 - Input Capture Register Low Byte Timer/Counter3 - Counter Register High Byte Timer/Counter3 - Counter Register Low Byte FOC3A ICNC3 COM3A1 FOC3B ICES3 COM3A0 FOC3C COM3B1 WGM33 COM3B0 WGM32 COM3C1 CS32 COM3C0 CS31 WGM31 CS30 WGM30 DDISCE DDISCI RESET DCONNE DCONNI SOFEN TXOUTI RXSTALLI RXINI COM2B0 PDAT7:0 PERRE TXSTPE TXOUTE RXSTALLE RXINE INTFRQ7:0 DTSEQ1:0 PBK1:0 PEPNUM3:0 PEN NBUSYBK1:0 ALLOC WGM22 CS22 CS21 WGM21 CS20 WGM20 Timer/Counter1 - Output Compare Register C High Byte Timer/Counter1 - Output Compare Register C Low Byte Timer/Counter1 - Output Compare Register B High Byte Timer/Counter1 - Output Compare Register B Low Byte Timer/Counter1 - Output Compare Register A High Byte Timer/Counter1 - Output Compare Register A Low Byte Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte FOC1A ICNC1 COM1A1 ADC7D FOC1B ICES1 COM1A0 ADC6D FOC1C COM1B1 ADC5D WGM13 COM1B0 ADC4D WGM12 COM1C1 ADC3D CS12 COM1C0 ADC2D CS11 WGM11 AIN1D ADC1D CS10 WGM10 AIN0D ADC0D - 11 7593KS-AVR-11/09 Address (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) Name ADMUX ADCSRB ADCSRA ADCH ADCL Reserved Reserved XMCRB XMCRA Reserved Reserved TIMSK3 TIMSK2 TIMSK1 TIMSK0 Reserved Reserved PCMSK0 EICRB EICRA PCICR Reserved OSCCAL PRR1 PRR0 Reserved Reserved CLKPR WDTCSR SREG SPH SPL Reserved RAMPZ Reserved Reserved Reserved SPMCSR Reserved MCUCR MCUSR SMCR Reserved OCDR/ MONDR ACSR Reserved SPDR SPSR SPCR GPIOR2 GPIOR1 PLLCSR OCR0B OCR0A TCNT0 TCCR0B TCCR0A GTCCR EEARH EEARL EEDR EECR GPIOR0 EIMSK EIFR Bit 7 REFS1 ADHSM ADEN Bit 6 REFS0 ACME ADSC Bit 5 ADLAR ADATE Bit 4 MUX4 ADIF Bit 3 MUX3 ADIE Bit 2 MUX2 ADTS2 ADPS2 Bit 1 MUX1 ADTS1 ADPS1 Bit 0 MUX0 ADTS0 ADPS0 Page ADC Data Register High byte ADC Data Register Low byte XMBK SRE PCINT7 ISC71 ISC31 PRUSB PRTWI CLKPCE WDIF I SP15 SP7 SPMIE JTD OCDR7 ACD SPIF SPIE SRL2 PCINT6 ISC70 ISC30 PRTIM2 WDIE T SP14 SP6 RWWSB OCDR6 ACBG WCOL SPE SRL1 ICIE3 ICIE1 PCINT5 ISC61 ISC21 PRTIM0 WDP3 H SP13 SP5 SIGRD OCDR5 ACO DORD SRL0 PCINT4 ISC60 ISC20 WDCE S SP12 SP4 RWWSRE PUD JTRF OCDR4 ACI MSTR SRW11 OCIE3C OCIE1C PCINT3 ISC51 ISC11 PRTIM3 PRTIM1 CLKPS3 WDE V SP11 SP3 BLBSET WDRF SM2 OCDR3 ACIE SPI Data Register CPOL CPHA SPR1 SPI2X SPR0 XMM2 SRW10 OCIE3B OCIE2B OCIE1B OCIE0B PCINT2 ISC50 ISC10 PRSPI CLKPS2 WDP2 N SP10 SP2 PGWRT BORF SM1 OCDR2 ACIC XMM1 SRW01 OCIE3A OCIE2A OCIE1A OCIE0A PCINT1 ISC41 ISC01 CLKPS1 WDP1 Z SP9 SP1 RAMPZ1 PGERS IVSEL EXTRF SM0 OCDR1 ACIS1 XMM0 SRW00 TOIE3 TOIE2 TOIE1 TOIE0 PCINT0 ISC40 ISC00 PCIE0 PRUSART1 PRADC CLKPS0 WDP0 C SP8 SP0 RAMPZ0 SPMEN IVCE PORF SE OCDR0 ACIS0 - Oscillator Calibration Register Monitor Data Register General Purpose I/O Register 2 General Purpose I/O Register 1 PLLP2 PLLP1 PLLP0 PLLE PLOCK Timer/Counter0 Output Compare Register B Timer/Counter0 Output Compare Register A Timer/Counter0 (8 Bit) FOC0A COM0A1 TSM FOC0B COM0A0 COM0B1 COM0B0 EEPROM Data Register INT7 INTF7 INT6 INTF6 EEPM1 INT5 INTF5 EEPM0 INT4 INTF4 EERIE INT3 INTF3 EEMPE INT2 INTF2 EEPE INT1 INTF1 EERE INT0 INTF0 General Purpose I/O Register 0 WGM02 CS02 CS01 WGM01 PSRASY CS00 WGM00 PSRSYNC EEPROM Address Register High Byte EEPROM Address Register Low Byte 12 AT90USB64/128 7593KS-AVR-11/09 AT90USB64/128 Address 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20) Name PCIFR Reserved Reserved TIFR3 TIFR2 TIFR1 TIFR0 Reserved Reserved Reserved PORTF DDRF PINF PORTE DDRE PINE PORTD DDRD PIND PORTC DDRC PINC PORTB DDRB PINB PORTA DDRA PINA Bit 7 PORTF7 DDF7 PINF7 PORTE7 DDE7 PINE7 PORTD7 DDD7 PIND7 PORTC7 DDC7 PINC7 PORTB7 DDB7 PINB7 PORTA7 DDA7 PINA7 Bit 6 PORTF6 DDF6 PINF6 PORTE6 DDE6 PINE6 PORTD6 DDD6 PIND6 PORTC6 DDC6 PINC6 PORTB6 DDB6 PINB6 PORTA6 DDA6 PINA6 Bit 5 ICF3 ICF1 PORTF5 DDF5 PINF5 PORTE5 DDE5 PINE5 PORTD5 DDD5 PIND5 PORTC5 DDC5 PINC5 PORTB5 DDB5 PINB5 PORTA5 DDA5 PINA5 Bit 4 PORTF4 DDF4 PINF4 PORTE4 DDE4 PINE4 PORTD4 DDD4 PIND4 PORTC4 DDC4 PINC4 PORTB4 DDB4 PINB4 PORTA4 DDA4 PINA4 Bit 3 OCF3C OCF1C PORTF3 DDF3 PINF3 PORTE3 DDE3 PINE3 PORTD3 DDD3 PIND3 PORTC3 DDC3 PINC3 PORTB3 DDB3 PINB3 PORTA3 DDA3 PINA3 Bit 2 OCF3B OCF2B OCF1B OCF0B PORTF2 DDF2 PINF2 PORTE2 DDE2 PINE2 PORTD2 DDD2 PIND2 PORTC2 DDC2 PINC2 PORTB2 DDB2 PINB2 PORTA2 DDA2 PINA2 Bit 1 OCF3A OCF2A OCF1A OCF0A PORTF1 DDF1 PINF1 PORTE1 DDE1 PINE1 PORTD1 DDD1 PIND1 PORTC1 DDC1 PINC1 PORTB1 DDB1 PINB1 PORTA1 DDA1 PINA1 Bit 0 PCIF0 TOV3 TOV2 TOV1 TOV0 PORTF0 DDF0 PINF0 PORTE0 DDE0 PINE0 PORTD0 DDD0 PIND0 PORTC0 DDC0 PINC0 PORTB0 DDB0 PINB0 PORTA0 DDA0 PINA0 Page Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and ST instructions, $20 must be added to these addresses. The AT90USB64/128 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 13 7593KS-AVR-11/09 5. Instruction Set Summary Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP EIJMP JMP RCALL ICALL EICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k Operands Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k Description Add two Registers Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned BRANCH INSTRUCTIONS Relative Jump Indirect Jump to (Z) Extended Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Extended Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Operation Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF - Rd Rd 0x00 - Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd 0xFF R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 (Rd x Rr) << Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 3 4 4 4 5 5 5 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ARITHMETIC AND LOGIC INSTRUCTIONS 1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1 PC PC + k + 1 PC Z PC (EIND:Z) PC k PC PC + k + 1 PC Z PC (EIND:Z) PC k PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 14 AT90USB64/128 7593KS-AVR-11/09 AT90USB64/128 Mnemonics BRVC BRIE BRID SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM ELPM ELPM ELPM Rd, Z Rd, Z+ Rd, Z Rd, Z+ Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Operands k k k P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b Description Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Operation if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 R0 (RAMPZ:Z) Rd (Z) Rd (RAMPZ:Z), RAMPZ:Z RAMPZ:Z+1 Flags None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None #Clocks 1/2 1/2 1/2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 BIT AND BIT-TEST INSTRUCTIONS Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG DATA TRANSFER INSTRUCTIONS Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Extended Load Program Memory Extended Load Program Memory Extended Load Program Memory 15 7593KS-AVR-11/09 Mnemonics SPM IN OUT PUSH POP NOP SLEEP WDR BREAK Operands Rd, P P, Rr Rr Rd Description Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Operation (Z) R1:R0 Rd P P Rr STACK Rr Rd STACK Flags None None None None None None #Clocks 1 1 2 2 1 1 1 N/A MCU CONTROL INSTRUCTIONS No Operation Sleep Watchdog Reset Break (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only None None None 16 AT90USB64/128 7593KS-AVR-11/09 AT90USB64/128 6. Ordering Information 6.1 AT90USB646 Speed(MHz) 20(3) Notes: Power Supply(V) 2.7-5.5 Ordering Code(2) AT90USB646-AU AT90USB646-MU USB Interface Device Package(1) MD PS Operating Range Industrial (-40 to +85C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also Halide free and fully Green. 3. See "Maximum speed vs. VCC" on page 400. MD 64 - Lead, 14x14 mm Body Size, 1.0mm Body Thickness 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 64 - Lead, 9x9 mm Body Size, 0.50mm Pitch Quad Flat No Lead Package (QFN) PS 17 7593KS-AVR-11/09 6.2 AT90USB647 Speed(MHz) 20(3) Notes: Power Supply(V) 2.7-5.5 Ordering Code(2) AT90USB647-AU AT90USB647-MU USB Interface USB OTG Package(1) MD PS Operating Range Industrial (-40 to +85C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also Halide free and fully Green. 3. See "Maximum speed vs. VCC" on page 400. MD 64 - Lead, 14x14 mm Body Size, 1.0mm Body Thickness 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 64 - Lead, 9x9 mm Body Size, 0.50mm Pitch Quad Flat No Lead Package (QFN) PS 18 AT90USB64/128 7593KS-AVR-11/09 AT90USB64/128 6.3 AT90USB1286 Speed(MHz) 20(3) Notes: Power Supply(V) 2.7-5.5 Ordering Code(2) AT90USB1286-AU AT90USB1286-MU USB Interface Device Package(1) MD PS Operating Range Industrial (-40 to +85C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also Halide free and fully Green. 3. See "Maximum speed vs. VCC" on page 400. MD 64 - Lead, 14x14 mm Body Size, 1.0mm Body Thickness 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 64 - Lead, 9x9 mm Body Size, 0.50mm Pitch Quad Flat No Lead Package (QFN) PS 19 7593KS-AVR-11/09 6.4 AT90USB1287 Speed(MHz) 20(3) Notes: Power Supply(V) 2.7-5.5 Ordering Code(2) AT90USB1287-AU AT90USB1287-MU USB Interface Host (OTG) Package(1) MD PS Operating Range Industrial (-40 to +85C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also Halide free and fully Green. 3. See "Maximum speed vs. VCC" on page 400. MD 64 - Lead, 14x14 mm Body Size, 1.0mm Body Thickness 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 64 - Lead, 9x9 mm Body Size, 0.50mm Pitch Quad Flat No Lead Package (QFN) PS 20 AT90USB64/128 7593KS-AVR-11/09 AT90USB64/128 6.5 TQFP64 21 7593KS-AVR-11/09 22 AT90USB64/128 7593KS-AVR-11/09 AT90USB64/128 6.6 QFN64 23 7593KS-AVR-11/09 24 AT90USB64/128 7593KS-AVR-11/09 AT90USB64/128 7. Errata 8. AT90USB1287/6 Errata. 8.1 AT90USB1287/6 Errata History Silicon Release First Release 90USB1286-16MU 90USB1287-16AU Date Code up to 0714 and lots 0735 6H2726* from Date Code 0722 to 0806 except lots 0735 6H2726* Date Code from 0814 90USB1287-16MU Date Code up to 0648 Date Code from 0709 to 0801 except lots 0801 7H5103* Lots 0801 7H5103* and Date Code from 0814 Date Code up to 0701 Date Code from 0714 to 0810 except lots 0748 7H5103* Lots 0748 7H5103* and Date Code from 0814 Second Release Third Release Note `*' means a blank or any alphanumeric string 8.2 AT90USB1287/6 First Release * Incorrect CPU behavior for VBUSTI and IDTI interrupts routines * USB Eye Diagram violation in low-speed mode * Transient perturbation in USB suspend mode generates over consumption * VBUS Session valid threshold voltage * USB signal rate * VBUS residual level * Spike on TWI pins when TWI is enabled * High current consumption in sleep mode * Async timer interrupt wake up from sleep generate multiple interrupts 9. Incorrect CPU behavior for VBUSTI and IDTI interrupts routines The CPU core may incorrectly execute the interrupt vector related to the VBUSTI and IDTI interrupt flags. Problem fix/workaround Do not enable these interrupts, firmware must process these USB events by polling VBUSTI and IDTI flags. 8. USB Eye Diagram violation in low-speed mode The low to high transition of D- violates the USB eye diagram specification when transmitting with low-speed signaling. Problem fix/workaround None. 7. Transient perturbation in USB suspend mode generates overconsumption In device mode and when the USB is suspended, transient perturbation received on the USB lines generates a wake up state. However the idle state following the perturbation does 25 7593KS-AVR-11/09 not set the SUSPI bit anymore. The internal USB engine remains in suspend mode but the USB differential receiver is still enabled and generates a typical 300A extra-power consumption. Detection of the suspend state after the transient perturbation should be performed by software (instead of reading the SUSPI bit). Problem fix/workaround USB waiver allows bus powered devices to consume up to 2.5mA in suspend state. 6. VBUS Session valid threshold voltage The VSession valid threshold voltage is internally connected to VBus_Valid (4.4V approx.). That causes the device to attach to the bus only when Vbus is greater than VBusValid instead of V_Session Valid. Thus if VBUS is lower than 4.4V, the device is detached. Problem fix/workaround According to the USB power drop budget, this may require connecting the device toa root hub or a self-powered hub. 5. UBS signal rate The average USB signal rate may sometime be measured out of the USB specifications (12MHz 30kHz) with short frames. When measured on a long period, the average signal rate value complies with the specifications. This bit rate deviation does not generates communication or functional errors. Problem fix/workaround None. 4. VBUS residual level In USB device and host mode, once a 5V level has been detected to the VBUS pad, a residual level (about 3V) can be measured on the VBUS pin. Problem fix/workaround None. 3. Spike on TWI pins when TWI is enabled 100 ns negative spike occurs on SDA and SCL pins when TWI is enabled. Problem Fix/workaround No known workaround, enable AT90USB64/128 TWI first versus the others nodes of the TWI network. 2. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected mode, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem Fix/workaround Before entering sleep, interrupts not used to wake up the part from the sleep mode should be disabled. 1. Asynchronous timer interrupt wake up from sleep generates multiple interrupts 26 AT90USB64/128 7593KS-AVR-11/09 AT90USB64/128 If the CPU core is in sleep and wakes-up from an asynchronous timer interrupt and then go back in sleep again it may wake up multiple times. Problem Fix/workaround A software workaround is to wait with performing the sleep instruction until TCNT2>OCR2+1. 27 7593KS-AVR-11/09 8.3 AT90USB1287/6 Second Release * Incorrect CPU behavior for VBUSTI and IDTI interrupts routines * USB Eye Diagram violation in low-speed mode * Transient perturbation in USB suspend mode generates over consumption * VBUS Session valid threshold voltage * Spike on TWI pins when TWI is enabled * High current consumption in sleep mode * Async timer interrupt wake up from sleep generate multiple interrupts 7. Incorrect CPU behavior for VBUSTI and IDTI interrupts routines The CPU core may incorrectly execute the interrupt vector related to the VBUSTI and IDTI interrupt flags. Problem fix/workaround Do not enable these interrupts, firmware must process these USB events by polling VBUSTI and IDTI flags. 6. USB Eye Diagram violation in low-speed mode The low to high transition of D- violates the USB eye diagram specification when transmitting with low-speed signaling. Problem fix/workaround None. 5. Transient perturbation in USB suspend mode generates overconsumption In device mode and when the USB is suspended, transient perturbation received on the USB lines generates a wake up state. However the idle state following the perturbation does not set the SUSPI bit anymore. The internal USB engine remains in suspend mode but the USB differential receiver is still enabled and generates a typical 300A extra-power consumption. Detection of the suspend state after the transient perturbation should be performed by software (instead of reading the SUSPI bit). Problem fix/workaround USB waiver allows bus powered devices to consume up to 2.5mA in suspend state. 4. VBUS Session valid threshold voltage The VSession valid threshold voltage is internally connected to VBus_Valid (4.4V approx.). That causes the device to attach to the bus only when Vbus is greater than VBusValid instead of V_Session Valid. Thus if VBUS is lower than 4.4V, the device is detached. Problem fix/workaround According to the USB power drop budget, this may require connecting the device toa root hub or a self-powered hub. 3. Spike on TWI pins when TWI is enabled 100 ns negative spike occurs on SDA and SCL pins when TWI is enabled. 28 AT90USB64/128 7593KS-AVR-11/09 AT90USB64/128 Problem Fix/workaround No known workaround, enable AT90USB64/128 TWI first versus the others nodes of the TWI network. 2. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected mode, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem Fix/workaround Before entering sleep, interrupts not used to wake up the part from the sleep mode should be disabled. 1. Asynchronous timer interrupt wake up from sleep generates multiple interrupts If the CPU core is in sleep and wakes-up from an asynchronous timer interrupt and then go back in sleep again it may wake up multiple times. Problem Fix/workaround A software workaround is to wait with performing the sleep instruction until TCNT2>OCR2+1. 29 7593KS-AVR-11/09 8.4 AT90USB1287/6 Third Release * Incorrect CPU behavior for VBUSTI and IDTI interrupts routines * Transient perturbation in USB suspend mode generates over consumption * Spike on TWI pins when TWI is enabled * High current consumption in sleep mode * Async timer interrupt wake up from sleep generate multiple interrupts 5. Incorrect CPU behavior for VBUSTI and IDTI interrupts routines The CPU core may incorrectly execute the interrupt vector related to the VBUSTI and IDTI interrupt flags. Problem fix/workaround Do not enable these interrupts, firmware must process these USB events by polling VBUSTI and IDTI flags. 4. Transient perturbation in USB suspend mode generates overconsumption In device mode and when the USB is suspended, transient perturbation received on the USB lines generates a wake up state. However the idle state following the perturbation does not set the SUSPI bit. The internal USB engine remains in suspend mode but the USB differential receiver is still enabled and generates a typical 300A extra-power consumption. Detection of the suspend state after the transient perturbation should be performed by software (instead of reading the SUSPI bit). Problem fix/workaround USB waiver allows bus powered devices to consume up to 2.5mA in suspend state. 3. Spike on TWI pins when TWI is enabled 100 ns negative spike occurs on SDA and SCL pins when TWI is enabled. Problem Fix/workaround No known workaround, enable AT90USB64/128 TWI first, before the others nodes of the TWI network. 2. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected mode, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem Fix/workaround Before entering sleep, interrupts not used to wake up the part from sleep mode should be disabled. 1. Asynchronous timer interrupt wake up from sleep generates multiple interrupts If the CPU core is in sleep mode and wakes-up from an asynchronous timer interrupt and then goes back into sleep mode, it may wake up multiple times. Problem Fix/workaround 30 AT90USB64/128 7593KS-AVR-11/09 AT90USB64/128 A software workaround is to wait beforeperforming the sleep instruction: until TCNT2>OCR2+1. 9. AT90USB647/6 Errata. * Incorrect interrupt routine exection for VBUSTI, IDTI interrupts flags * USB Eye Diagram violation in low-speed mode * Transient perturbation in USB suspend mode generates over consumption * Spike on TWI pins when TWI is enabled * High current consumption in sleep mode * Async timer interrupt wake up from sleep generate multiple interrupts 6. Incorrect CPU behavior for VBUSTI and IDTI interrupts routines The CPU core may incorrectly execute the interrupt vector related to the VBUSTI and IDTI interrupt flags. Problem fix/workaround Do not enable these interrupts, firmware must process these USB events by polling VBUSTI and IDTI flags. 5. USB Eye Diagram violation in low-speed mode The low to high transition of D- violates the USB eye diagram specification when transmitting with low-speed signaling. Problem fix/workaround None. 4. Transient perturbation in USB suspend mode generates overconsumption In device mode and when the USB is suspended, transient perturbation received on the USB lines generates a wake up state. However the idle state following the perturbation does not set the SUSPI bit anymore. The internal USB engine remains in suspend mode but the USB differential receiver is still enabled and generates a typical 300A extra-power consumption. Detection of the suspend state after the transient perturbation should be performed by software (instead of reading the SUSPI bit). Problem fix/workaround USB waiver allows bus powered devices to consume up to 2.5mA in suspend state. 3. Spike on TWI pins when TWI is enabled 100 ns negative spike occurs on SDA and SCL pins when TWI is enabled. Problem Fix/workaround No known workaround, enable AT90USB64/128 TWI first versus the others nodes of the TWI network. 2. High current consumption in sleep mode 31 7593KS-AVR-11/09 If a pending interrupt cannot wake the part up from the selected mode, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem Fix/workaround Before entering sleep, interrupts not used to wake up the part from the sleep mode should be disabled. 1. Asynchronous timer interrupt wake up from sleep generates multiple interrupts If the CPU core is in sleep and wakes-up from an asynchronous timer interrupt and then go back in sleep mode again it may wake up several times. Problem Fix/workaround A software workaround is to wait with performing the sleep instruction until TCNT2>OCR2+1. 32 AT90USB64/128 7593KS-AVR-11/09 AT90USB64/128 10. Datasheet Revision History for AT90USB64/128 Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 10.1 Changes from 7593A to 7593B 1. Changed default configuration for fuse bytes and security byte. 2. Suppression of timer 4,5 registers which does not exist. 3. Updated typical application schematics in USB section 10.2 Changes from 7593B to 7593C 1. Update to package drawings, MQFP64 and TQFP64. 10.3 Changes from 7593C to 7593D 1. For further product compatibility, changed USB PLL possible prescaler configurations. Only 8MHz and 16MHz crystal frequencies allows USB operation (See Table 6-11 on page 49). 10.4 Changes from 7593D to 7593E 1. Updated PLL Prescaler table: configuration words are different between AT90USB64x and AT90USB128x to enable the PLL with a 16 MHz source. 2. Cleaned up some bits from USB registers, and updated information about OTG timers, remote wake-up, reset and connection timings. 3. Updated clock distribution tree diagram (USB prescaler source and configuration register). 4. Cleaned up register summary. 5. Suppressed PCINT23:8 that do not exist from External Interrupts. 6. Updated Electrical Characteristics. 7. Added Typical Characteristics. 8. Update Errata section. 10.5 Changes from 7593E to 7593F 1. Removed 'Preliminary' from document status. 2. Clarification in Stand by mode regarding USB. 10.6 Changes from 7593F to 7593G 1. Updated Errata section. 10.7 Changes from 7593G to 7593H 1. Added Signature information for 64K devices. 2. Fixed figure for typical bus powered application 3. Added min/max values for BOD levels 4. Added ATmega32U6 product 5. Update Errata section 6. Modified descriptions for HWUPE and WAKEUPE interrupts enable (these interrupts should be enabled only to wake up the CPU core from power down mode). 33 7593KS-AVR-11/09 7. Added description to access unique serial number located in Signature Row see "Reading the Signature Row from Software" on page 360. 10.8 Changes from 7593H to 7593I 1. Updated Table 8-2 in "Brown-out Detection" on page 60. Unused BOD levels removed. 10.9 Changes from 7593I to 7593J 1. Updated Table 8-2 in "Brown-out Detection" on page 60. BOD level 100 removed. 2. Updated "Ordering Information" on page 435. 3. Removed ATmega32U6 errata section. 10.10 Changes from 7593J to 7593K 1. Corrected Figure 5-7 on page 33, Figure 5-8 on page 33 and Figure 5-9 on page 34. 2. Corrected ordering information for Section 6.3 "AT90USB1286" on page 19, Section 6.4 "AT90USB1287" on page 20 andSection 6.2 "AT90USB647" on page 18. 3. Removed the ATmega32U6 device and updated the datasheet accordingly. 4. Updated Assembly Code Exemple in "Watchdog Reset" on page 61. 34 AT90USB64/128 7593KS-AVR-11/09 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) 2009 Atmel Corporation. All rights reserved. Atmel(R), Atmel logo and combinations thereof, AVR(R) and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others 7593KS-AVR-11/09 |
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